Senior Analog Layout Engineer

Yokneam · Full-time

About The Position

Chain reaction is looking for a Senior Analog Layout Engineer, someone who is excited to join a growing design group responsible for handling challenge in the cutting-edge technologies and silicon process nodes.

As a team member you will be working on Layout designs for Chain-reaction Cryptography ASICs such as PLLs, VCOs, Sense -Amps, High-Speed circuits, I/Os, ESD and much more.

What you will be doing:

  • Layout design of sensitive analog circuits where you will need to bring state-of-the-art solutions.
  • In close co-operation with the Circuit designer, review and analyse complex analog schematics for layout implementation.
  • Ensuring layout design’s best functionality and quality by performing all relevant checks like parasitic checks, IR drop and Electromigration, noise and DFM.
  • Performing post-layout iterations to ensure the best results.

Requirements

What we need to see from you:


  • Electronics Practical Engineer certificate or a B.Sc. in Electrical Engineering.
  • Have a minimum 5 years of a relevant Analog layout experience.
  • Experience in advanced technology nodes like 7nm and below would be a huge advantage.
  • Proven understanding of Analog Layout concepts in submicron FinFet technologies – 16nm and below.
  • You can work effectively in a team, good interpersonal skills, enthusiasm and positive energy.

 

How to stand out in the crowd:

  • Proficiency in scripting languages like bash, Perl, Skill etc.
  • Experience in Full-Chip level integration.
  • Prior experience with Cadence virtuoso environment.

 

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